m e m s ic m x c 6202g/ h / m / n r e v.b page 1 of 1 0 11/10/2005 low power, low profile 2 g dual axis accelerometer with i 2 c interface mxc6202g/h/m/n features rohs compliant i 2 c slave, fast ( 400 khz .) mode i n terface 1.8v compati b l e io embedded pow er up/dow n and self-test function on-chip temperature sensor available eight customer defined 7-bit addresses 2.7 v to 3.6 v single s upply continuous operation monolithic cmos ic low power consumption: ty pically <2 ma @ 3.0 v reso lutio n better tha n 1 milli- g on chi p mi xed si gnal processi ng >50,000 g shock survi val rati ng l o w profi l e l cc package: 5mm x 5mm x 1.55mm applications information appliances ? c e l l phones, pda?s, c o m put er peri pheral s , m ouse, sm art pens consumer ? lc d project ors, pedom et ers, b l ood pressure monitor, digital cam e ras gaming ? joystick/rf interface/menu selection/tilt sensing gps ? electro n i c co m p ass tilt co rrectio n , dead r eckoni ng assi st general description the m x c 6202g/ h / m / n are l o w cost , dual axi s accelerom eters fabricated on a standard, subm icron cmos p r o cess. it is a co m p lete sen s in g system with o n - ch ip m i xed si gnal processi ng and i n t e grat ed i 2 c bus, al l o wi ng the device to be connected di rectly to a m i croprocessor el i m i n at i ng t h e need for a/ d convert ers or t i m i ng resources. the mxc6202g/h/m/n m easures acceleration with a full-scale range of 2 g an d a sen s itiv ity o f 512count s/ g (g/ m ) or 128count s/ g (h/ n ) @3.0 v at 25 c . it can m easure both dynam i c acceleration (e.g. vibration) and static acceleration (e.g. gravity). the m x c 6202g/ h / m / n desi gn i s based on heat convect i on and requi res no sol i d proof m a ss. vdd vre f cl k tp pd cl k cl k te mp cl k clk te m p a/d clk clk t emp clk te m p comp. tem p co mp . x ai x s y a i x s cl k h e at er con t ro l tem p no c o nn ec t no c o nn ec t scl sda iic con v e r to r a/d te mpe r at ure sens o r inte rna l o s c ill at or co a r s e g a in ad j. fin e g a in ad j. gnd ac c e lera ti on sen s o r coa r s e ga in a dj. fin e g a in ad j. mxc6202g/h/m/n functional block diagram th is d e sig n elim in ates th e stictio n p r o b l em s asso ciated with l e gacy t echnol ogi es and provi des shock survi v al great er t h an 50,000 g?s. mem s ic?s solid state design leads to sig n i fican tly lo wer failu re rates in cu sto m er ap p licatio n s and l o wer l o ss due t o handl i ng duri ng m a nufact uri ng and assem b ly processes the m x c 6202g/ h / m / n i s packaged i n a herm et i cal l y sealed, low profile lcc surface m ount package (5 m m x 5 m m x 1.55 m m ) and i s avai l a bl e i n operat i ng t e m p erat ure ranges of 0 c to +7 0 c (g/ h ) and-40 c to +8 5 c(m/n). the m x c 6202g/ h / m / n provi des t w o i 2 c di gi t a l out put s wi t h 400 khz, fast m ode operat i on. the maximum noise floor is 1 m g / hz al l o w i ng si gnal s belo w 1 milli- g to be resolved at 1 hz bandwidth inform ation furnished by memsic is believe d to be accurate and reliable. however, no responsibility is assum e d by me msic for its use, or for any infringem e nts of patents or other rights of th ird parties w h ich m a y result from its use. n o license is granted by im plication or otherw ise under any patent or patent rights of me msic. ? memsic, inc. 800 turnpik e st . , suit e 202, nort h andover, ma 01845 tel: 978. 738. 0900 f ax: 978. 738. 0196 www. m e m s i c . c o m
m e m s ic m x c 6202g/ h / m / n rev.b page 2 of 10 11 /10/2005 electrical characteristics (m eas urem ents @ 25 c, acceleration = 0 g unless otherwise noted; v dd = 3.0v unless otherwis e s p ecified) p a r a m e t e r c o n d i t i o n s m i n t y p m a x u n i t s measurem ent range 1 each axis 2.0 g n o n lin earity best fit straig h t lin e 0 . 5 1 . 0 % of fs alig n m en t erro r 2 1.0 d e g r e e s tran sv erse sen s itiv ity 3 2.0 % 4 8 6 5 1 2 5 3 8 count s/ g sen s itiv ity m x c 6202g/ m m x c 6202h/ n 1 1 8 1 2 8 1 3 8 count s/ g sen s itiv ity ch an g e ov er tem p eratu r e ? from 25 c m x c 6202g/ h m x c 6202m / n -10 -15 +8 +10 % % zero g offset b i as level m x c 6202g/ m m x c 6202h/ n 1996 492 2048 512 2100 532 count s count s zero g offset tc ? from 25 c 0 . 8 m g / c tout m x c 6202g/ m m x c 6202h/ n 2550 635 2710 675 2870 715 count s count s tout sensitivity mxc6202g/m m x c 6202h/ n 2.00 0.48 2.33 0.58 2.60 0.68 count s/ c count s/ c n oi se densi t y , r m s wi t h i n 20hz 0.7 1.0 m g / hz r e sol u t i on @ 1hz. b w 0.5 1.0 m g frequency r e sponse @ -3db 15 17 19 hz sel f-t est 1 . 7 2 . 2 2 . 7 g output drive capability @ 2.7 v ? 3.6 v 100 a turn-on tim e 4 7 5 1 0 0 m s operat i ng vol t a ge r a nge 2.7 3.0 3.6 v suppl y c u rrent 1.8 2.5 m a power down current 1.0 a operat i ng tem p erat ure r a nge m x c 6202g/ h m x c 6202m / n 0 -40 + 7 0 +85 c c notes: 1 guaranteed by m easurem ent of initial offset and sensitivity 2 alignm ent error is specif i ed as the angle between the true and indicated axis of sensitivity 3 cross axis sensitivity is the algebr aic sum of the alignm ent and the inherent sensitivity errors 4 o u tput settled to w ithin 17m g
m e m s ic m x c 6202g/ h / m / n rev.b page 3 of 10 11 /10/2005 i 2 c interface i/o characteristics p a r a m e t e r s y m b o l test c o n d i t i o n m i n . t y p . m a x . unit logi c input low level v il - 0 . 5 0 . 6 v logi c input hi gh level v ih 1 . 4 v hysteresis of schm itt input v hy s 0 . 2 v logi c out put low level v ol 0 . 4 input leakage c u rrent i i 0.1vdd m e m s ic m x c 6202g/ h / m / n rev.b page 4 of 10 11 /10/2005 absolute max i mum ratings* suppl y vol t a ge (v dd ) ??????...-0.5 v to +7.0v storage tem p erature ???.????-65 c t o +150 c acceleration ??????????????..50,000 g *stresses above those liste d under a b solute maxim u m ratings m a y cause perm anent dam a ge to the device. t h is is a stress rating only ; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not im p lied. e xposure to absolute m a xim u m rating conditions for extended periods m a y affect device reliability . pin description: lcc-8 package p i n n a m e d e s c r i p t i o n 1 nc do not connect 2 c o m c onnect ed t o ground 3 gnd connect ed t o ground 4 test do not connect 5 vdd2 power suppl y for i 2 c bus 6 sc l seri al c l ock li ne for i 2 c bus 7 sda serial data line for i 2 c bus 8 v dd 2.7 v t o 3.6 v ordering guide mx c6202x gp all parts are shipped in tape and reel packaging. caution: esd (electrostatic discharge) sensitive device. note: the memsic logo?s arrow indicates the -x sensing direction of the device. the +y sensing direction is rotated 90 away from the +x direction following the right-hand rule. small circle indicates pin one (1). p ackage ty pe: c o d e t y p e p l c c 8 rohs com p liant b l c c 8 , p b - f r e e rohs com p liant address code: 0~7 n u m b e r a d d r e s s 0 2 0 h 1 2 2 h 2 2 4 h 3 2 6 h 4 2 8 h 5 2 a h 6 2 c h 7 2 e h p e rform ance grade: c o d e t e m p r e s o l u t i o n g 0~70 c 4096counts h 0~70 c 1024counts m -40~85 c 4096counts n -40~85 c 1024counts
m e m s ic m x c 6202g/ h / m / n rev.b page 5 of 10 11 /10/2005 typical characteristics, % of units (@ 25 c, v dd = 3v) offse t x di st ri b u t i o n 0% 10% 20% 30% 40% 50% 60% - 9 6 - 76 - 5 6 - 36 - 1 5 5 25 46 66 86 offse t (mg) offse t y di st ri b u t i o n 0% 10% 20% 30% 40% 50% 60% - 9 6 - 76 - 5 6 - 36 - 1 5 5 25 46 66 86 offse t (mg) 0g offsety deviation to target 0g offsetx deviation to target s e ns itiv ity x d i s t r i butio n 0% 5% 10% 15% 20% 25% 30% 35% - 4 8- 3 8 - 2 8- 1 8 - 8 3 1 3 2 3 3 3 4 3 se n (mg) s e ns itiv i ty y d i s t r i butio n 0% 5% 10% 15% 20% 25% 30% 35% -4 8 - 3 8 -2 8 - 1 8 -8 3 1 3 2 3 3 3 4 3 se n (mg) sensitivity x deviation to target sensitivity y deviation to target
m e m s ic m x c 6202g/ h / m / n rev.b page 6 of 10 11 /10/2005 over temperature characteristics to u t v s . tem p 2500 2550 2600 2650 2700 2750 2800 2850 2900 2950 3000 - 5 0 - 10 30 70 110 t( c ) t o ut s e ns itiv i ty d i s t r i butio n 0% 5% 10% 15% 20% 25% 2.02 2.11 2.20 2. 29 2.38 2.47 2.56 to u t tc n o r m al iz e d s e ns itiv ity y v s . t e m p 0.88 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 - 5 0 - 10 30 70 110 t( c ) offse t x t c di st ri b u t i o n 0% 5% 10% 15% 20% 25% 30% - 1 .9 - 1 .3 - 0 .7 - 0 .1 0.5 1 .1 1.7 tc ( m g / c ) offse t y t c di st ri b u t i o n 0% 5% 10% 15% 20% 25% 30% - 1 .9 - 1 .3 - 0 .7 - 0 .1 0.5 1 .1 1.7 tc ( m g / c ) n o r m al iz e d s e ns itiv ity x v s . t e m p 0.88 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 - 5 0 - 10 30 70 110 t( c )
m e m s ic m x c 6202g/ h / m / n rev.b page 7 of 10 11 /10/2005 acceleration in any direction will disturb the tem p erature profi l e , due t o free convect i on heat t r ansfer, causi ng i t t o be asy m m e t r i cal . the t e m p erat ure, and hence vol t a ge out put o f th e fo u r th erm o p iles will th en b e d i fferen t . th e d i fferen tial v o ltag e at th e th erm o p ile o u t p u t s is d i rectly proportional to the acceleration. there are two identical acceleration signal paths on the accelerom eter, one to m easure acceleration in the x-axis and one to m easure acceleration in the y-axis. please visit the memsic website at www.m e m s ic.com for a picture/graphic descri pt i on of t h e free convect i on heat t r ansfer pri n ci pl e. theory of operation the memsic device is a com p lete dual-axis acceleration m easu r em en t system fab r icated o n a m o n o lith ic cmos ic process. the devi ce operat i on i s based on heat t r ansfer by natural convection and opera tes like other accelerom eters except that the proof m a ss in the m e m s ic sensor i s a gas. a sin g l e h eat so u r ce, cen tered in th e silico n ch ip is suspended across a cavity. equally spaced alum inum /polysilicon therm opiles (groups of t h erm o coupl es) are l o cat ed equi di st ant l y on al l four si des of the heat source (dual axis). under zero acceleration, a t e m p erat ure gradi e nt i s sy m m e t r i cal about t h e heat source, so th at th e tem p eratu r e is th e sam e at all fo u r th erm o p iles, causi ng t h em t o out put t h e sam e vol t a ge. mx c6202g/ h / m / n pin de script ions v dd ? thi s i s t h e suppl y i nput for t h e ci rcui t s and t h e sensor heater in the accelerom eter . the dc vol t a ge shoul d be bet w een 2.7 and 3.6 vol t s . r e fer t o t h e sect i on on pc b l a y out and fabri cat i on suggest i ons for gui dance on ext e rnal part s and connect i ons recom m e nded. gnd ? thi s i s t h e ground pi n for t h e accelerom eter . com ? thi s pi n shoul d be connect ed t o ground. test ? do not c onnect , fact ory use onl y . vdd2 ? thi s pi n i s t h e i 2 c i nput di gi t a l power suppl y , t h e vol t a ge on t h i s pi n det e rm i n es t h e i 2 c bus l ogi c vol t a ge, an d is 1 . 8 v co m p atib le. no te: th e v o ltag e o n th is p i n shoul d never go hi gher t h an t h e vol t a ge on v dd , if vdd2 has a l o wer power suppl y vol t a ge t h an v dd , power shoul d be appl i e d t o v dd first. sda ? thi s pi n i s t h e i 2 c serial d a ta lin e, an d o p e rates in fast (400 khz.) m ode. scl ? thi s pi n i s t h e i 2 c seri al cl ock l i n e, and operat e s i n fast (400 khz.) m ode. discussion of tilt applications and resolution tilt applica t io ns: one of t h e m o st popul ar appl i cat i ons of the memsic accelerom eter product line is in tilt/inclination m easurem ent. an accelerom eter uses the force of gravi t y as an i nput t o det e rm i n e t h e i n cl i n at i on angl e of an object . a memsic accelerom eter is m o st sensitive to changes in position, or tilt, when the accelerom eter?s sensitive axis is p e rp en d i cu lar to th e fo rce o f g r av ity, o r p a rallel to th e earth?s surface. sim ilarly, wh en the accelerom eter?s axis is p a rallel to th e fo rce o f g r av ity (p erp e n d i cu lar to th e earth ? s surface), it is least sensitiv e to changes in tilt. fo llo win g tab l e an d fig u r e h e lp illu strate th e o u t p u t ch an g e s in th e x- an d y-ax es as th e u n it is tilted fro m +9 0 to 0 . notice that when one axis has a sm all change in o u t p u t p e r d e g r ee o f tilt (in m g ), t h e second axi s has a l a rge ch an g e in o u t p u t p e r d e g r ee o f tilt. th e co m p lem e n t ary nature of these two signals perm its low cost accurate tilt sensi ng t o be achi e ved wi t h t h e m e m s ic devi ce (reference appl i cat i on not e an-00m x-007). m e m s i c accelerom eter position relative to gravity x - a x i s y - a x i s x-axis orien t atio n to earth?s surface (deg.) x output ( g ) c h ange per deg. o f tilt (m g ) y output ( g ) c h ange per deg. o f tilt (m g ) 9 0 1 . 0 0 0 0 . 1 5 0 . 0 0 0 1 7 . 4 5 8 5 0 . 9 9 6 1 . 3 7 0 . 0 8 7 1 7 . 3 7 8 0 0 . 9 8 5 2 . 8 8 0 . 1 7 4 1 7 . 1 6 7 0 0 . 9 4 0 5 . 8 6 0 . 3 4 2 1 6 . 3 5 6 0 0 . 8 6 6 8 . 5 9 0 . 5 0 0 1 5 . 0 4 4 5 0 . 7 0 7 1 2 . 2 3 0 . 7 0 7 1 2 . 2 3 3 0 0 . 5 0 0 1 5 . 0 4 0 . 8 6 6 8 . 5 9 2 0 0 . 3 4 2 1 6 . 3 5 0 . 9 4 0 5 . 8 6 1 0 0 . 1 7 4 1 7 . 1 6 0 . 9 8 5 2 . 8 8 5 0 . 0 8 7 1 7 . 3 7 0 . 9 9 6 1 . 3 7 0 0 . 0 0 0 1 7 . 4 5 1 . 0 0 0 0 . 1 5 changes in tilt for x- and y - axes
m e m s ic m x c 6202g/ h / m / n rev.b page 8 of 10 11 /10/2005 resolution the accelerom eter resolution is lim ited by noise. the o u t p u t n o i se will v a ry with th e m easu r em en t b a n d w id th . w i t h t h e reduct i on of t h e bandwi d t h , by appl y i ng an ex tern al lo w p a ss filter, th e o u t p u t n o i se d r o p s . red u c tio n o f b a n d w id th will im p r o v e th e sig n a l to n o i se ratio an d th e resol u t i on. the out put noi se scal es di rect l y wi t h t h e square root of t h e m easurem ent bandwi d t h . the m a xi m u m am pl i t ude of t h e noi se, i t s peak- t o - peak val u e, approxi m a t e l y defi nes t h e worst case resol u t i on of t h e m easu r em en t. w ith a sim p le rc lo w p a ss filter, th e rm s n o i se is calcu lated as fo llo ws: noise (m g rm s) = noise(m g / hz ) * ) 6 . 1 * ) ( ( hz bandwidth the peak-t o-peak noi se i s approxi m a t e l y equal t o 6.6 t i m es the rm s value (for an averag e uncert a i n t y of 0.1%). hardware design consideration 1. one capaci t o r i s recom m e nded for best reject i on of power suppl y noi se (reference fi gure bel o w). the capaci t o r shoul d be l o cat ed as cl ose as possi bl e t o t h e devi ce suppl y pi n (v dd ). the capacitor lead length should be as short as possible, and a surface m ount capacitor is preferred. for typical applications, the capacitor can be ceram ic 0.1 f. pow e r suppl y noi se rej ect i o n 2. r obust l o w i nduct a nce ground wi ri ng shoul d be used. 3. c a re shoul d be t a ken t o ensure t h ere i s ?t herm al sy m m e t r y ? on t h e pc b i m m e di at el y surroundi ng t h e memsic device and that there is no significant heat source nearby . b a sed on t h e experi m e nt , wi t h a 120degc heat i ng source at 11m m away of m e m s ic d e v i ce, th e o ffset ch an g e will b e with in 5 m g . 4. a m e t a l ground pl ane shoul d be added di rect l y beneat h t h e m e m s ic devi ce. the si ze of t h e pl ane shoul d be si m i l a r t o t h e m e m s ic devi ce?s foot pri n t and be as t h i c k as possi bl e. 5. vi as can be added sy m m e t r i cal l y around t h e ground p l an e. th ese v i as will in crease th e th erm a l iso l atio n o f t h e devi ce from t h e rest of t h e pc b and i m prove perform ance. software design consideration in order t o furt her reduce t h e noi se on t h e i2c bus, we reco m m e n d to u s e th e fo llo win g so ftware lim iter filter in the acceleration signal process routine: int iaccreal[0x02];//real-tim e acceleration data array int iaccfilter;//filtered acceleration data softwarelim iterfilter() { i f (abs(i accr eal [0x00] -i accr eal [0x01] )<0x80) t h en iaccfilter=iaccreal[0x00]; i a ccr eal [0x01] = i a ccr eal [0x00] ; } i 2 c interface description a slave m ode i 2 c circu it h a s b een im p l em en ted in to th e mem s ic therm a l accelerom eter as a standard interface for cust om er appl i cat i ons. the a/ d convert er and m c u fu n c tio n a lity h a v e b een ad d e d to th e mem s ic sen s o r , thereby increasing ease-of-use, and lowering power consum pt i on, foot pri n t and t o t a l sol u t i on cost . the i 2 c (or int e r ic bus) i s an i ndust r y st andard bi - directional two-wire interface bus. a m a ster i 2 c device can operat e r e ad/ w r ite cont rol s t o an unl i m i t e d num ber of devi ces on t h e bus by proper addressi ng. the m e m s i c accelerom eter operates only in a slave m ode, i.e. only respondi ng t o cal l s by a m a st er devi ce i 2 c bus characteristics i 2 c bus th e two wires in i 2 c b u s are called sda (serial d a ta lin e) and sc l (seri a l cl ock l i n e). in order for a dat a t r ansfer t o st art , t h e bus has t o be free, whi c h i s defi ned by bot h wi res i n a high out put st at e. due t o t h e open-drai n/ pul l - up resistor structure and wire -and operation, any device on th e b u s can p u ll lin es lo w an d o v e rwrite a high sig n a l. the dat a on t h e sda l i n e has t o be st abl e duri ng t h e high peri od of t h e sc l l i n e. in ot her words, val i d dat a can onl y change when the scl line is low .
i2c bus data transfer m e m s ic m x c 6202g/ h / m / n rev.b page 9 of 10 11 /10/2005 a d a ta tran sfer is started with a ?start? co n d itio n an d ended wi t h a ?stop? condi t i on. a ?star t ? condi t i on i s defi ned by a high t o low t r ansi t i on on t h e sda l i n e whi l e sc l l i n e i s high. a ?stop? condi t i on i s defi ned by a low to high tran sitio n o n th e sda lin e wh ile scl lin e is high. all d a ta tran sfer in i 2 c sy st em i s 8-bi t s l ong. each by t e has t o be fol l o wed by an acknowl e dge bi t . each dat a t r ansfer i nvol ves a t o t a l of 9 cl ock cy cl es. dat a i s tran sferred startin g with th e m o st sig n i fican t b it (msb). after a ?start? condition, m a ster device calls a specific slave device, in our case, th e mem s ic accelerom eter with a 7-bi t devi ce address. to avoi d pot ent i a l address confl i c t , ei t h er by ic s from ot her m a nufact urers or by ot her m e m s i c accelerom eters on the sam e bus, a total of 8 different addresses can be program m e d i n t o a m e m s i c devi ce at t h e factory. fo llo win g th e 7 - b it ad d r ess, th e 8 th b it d e term in es th e direction of data transfer: [1] for read and [0] for w r ite. aft e r bei ng addressed, t h e avai l a bl e m e m s i c device being called will re spond by an ?acknowledge? sig n a l, wh ich is p u llin g sda lin e low . in order to read an accelera tion signal, the m a ster device shoul d operat e a w r ite act i on wi t h a code of [xxxxxxx0] in to th e mem s ic d e v i ce 8 - b it in tern al reg i ster. b i t n a m e funct i o n 0 pd (power down) power down [1] / on [0] 1 st (self-test) self-test on [1] / off [0] 2 b g tst (bandgap t e st ) b a ndgap t e st [1] / norm a l [ 0] 3 t o e n (tem p e r a t u r e out enable) tem p out en [1] / di sabl e[0] th e st b it serv es as a self-test fu n c tio n to v e rify th e mem s ic accelerom eter is operating properly. bgtst is u s ed to calib rate th e tem p eratu r e o u t p u t sig n a l?s in itial offset . b y fl i ppi ng t h e b g tst bi t and t a ki ng t h e average of two read in g s , th e tem p eratu r e o u t p u t in itial o ffset will b e calib rated to with in d a tash eet sp ecificatio n s . aft e r wri t i ng code of [xxxxxxx0] i n t o t h e cont rol regi st er, if a ?read? signal is received, during next 9 clock cycles, th e mem s ic d e v i ce b e in g called will tran sfer 8 - b its o f d a ta to th e i 2 c bus. if an ?acknowl e dge? by m a st er devi ce i s received, the mem s ic device w ill continue to transfer the n e x t b y te. th e sam e p r o ced u r e rep eats u n til 5 b y tes o f d a ta are transferred to m a ster device. those 5 bytes of data are defi ned as fol l o wi ng (?t? i s t e m p erat ure out put ): 1. internal register 2. m s b x/ t axi s 3. lsb x/t axis 4. m s b y axi s 5. lsb y axi s even though each axis consists of two bytes, which are 16- bits of data, the actual accelerom eter resolution is lim ited to ei t h er 12 bi t s or 10 bi t s , whi c h depends on an i n t e rnal o u t p u t reg i ster refresh rate. un u s ed msb?s will b e sim p ly filled b y ?0 ?s. note that tem p erature output sh ares the sam e registers with x channel out put . c u st om er can sel ect whi c h si gnal needs t o be read out by usi ng toen bi t . r e sol u t i on 10 bi t s 12 bi t s r e freshi ng rat e 400hz 100hz zero-g offset 512 2048 the m a ster can stop slave data tr ansfer after any of the five by t e s by not sendi ng an acknowl e dge com m a nd and fol l o wed by a ?stop? condi t i on. data tran sfer power down mode the mem s ic accelerom eter can enter a power down m ode by t h e m a st er devi ce wri t i ng a code of [xxxxxxx1] i n t o t h e accelerom eter?s internal regi ster. a wake up operation is perform ed when the m a ster write s in to th e sam e reg i ster a code of [xxxxxxx0] . not e t h at t h e m x c 6202g/ h / m / n needs about 75m s (t y p i cal ) for power up t i m e. ex ample of data communication first cycle: start followed by a calling to slave address [0010xxx] t o w r ite (8 th sc l, sda keep l o w). [xxx] is det e rm i n ed by fact ory program m i ng, a t o t a l of 8 di fferent addresses are available. second cycle: after an acknow ledge signal is received by the m a ster device (mem sic device pulls sda line low duri ng 9 th sc l pul se), m a st er devi ce sends ?[00000000] ? as the target address to be written into. mem s ic device should acknowl e dge at t h e end (9 th scl p u l se). no te: sin ce m e m s i c devi ce has onl y one i n t e rnal regi st er t h at can be written into, user should al ways indicat e ?[00000000]? as th e write ad d r ess. third cycle: master device writes to in tern al mem s ic devi ce m e m o ry code ?[xxxxxxx0] ? as a wake-up cal l . the m e m s i c devi ce shoul d send acknowl e dge si gnal . a stop com m a nd i ndi cat es t h e end of wri t e operat i on. a 75m ss (t y p i cal ) wai t peri od shoul d be gi ven t o m e m s i c devi ce t o ret u rn from a power-down m ode. the del a y val u e depends on t h e t y pe of m e m s i c devi ce. general l y speaki ng, l o w power product s t e nd t o have l onger st art up t i m e.
m e m s ic m x c 6202g/ h / m / n rev.b page 10 of 10 11 /10/2005 fourth cycle: master de vi ce sends a star t com m a nd fol l o wed by cal l i ng m e m s i c devi ce address wi t h a w r ite (8 th sc l, sda keep l o w). an ?acknowl e dge? shoul d be sent by m e m s i c devi ce at t h e end. fifth cycle: master device writes to mem s ic device a ?[00000000] ? as t h e st art i ng address for whi c h i n t e rnal m e m o ry i s t o be read. si nce ?[00000000] ? i s t h e address of internal control register, read ing from this address can serve as a veri fi cat i on of operat i on and t o confi r m t h e wri t e com m a nd has been successful . not e : t h e st art i ng address i n principle can be any of the 5 addresses. for exam ple, user can st art read from address [0000001] , whi c h i s x channel msb. sixth cycle: master device cal l s m e m s i c devi ce address with a read (8 th scl cycle sda line high). mem s ic devi ce shoul d acknowl e dge at t h e end. seventh cycle: master de vice cycles scl line, first addressed m e m o ry dat a appears on sda l i n e. if i n st ep 7, ?[00000000] ? was sent , i n t e rnal cont rol regi st er dat a shoul d appear (i n t h e fol l o wi ng st eps, t h i s case i s assum e d). m a st er devi ce shoul d send acknowl e dge at t h e end. eighth cycle: master device c ont i nues cy cl e sc l l i n e, next by t e of i n t e rnal m e m o ry shoul d appear on sda l i n e (m sb of x channel ) . the i n t e rnal m e m o ry address poi nt er au to m a tically m o v e s to th e n e x t b y te. master acknowl e dges. ninth cycle: lsb of x channel. in the case that toen bit of internal register was set to ?1?, the msb and lsb of tout (t em perat u re) shoul d appear i n l a st t w o st eps. tenth cycle: msb of y channel. eleventh cycle: lsb of y channel. m a st er ends com m uni cat i ons by sendi ng no acknowl e dge and fol l o wed by a stop com m a nd. not e : i f m a t e r devi ce co n tin u e s to cycle scl lin e, th e m e m o ry p o i n t er will g o to si xt h and sevent h posi t i ons, whi c h al way s have ?[00000000]?. after seventh pos ition, pointer will go to zero again. opt i onal : m a st er powers down m e m s i c devi ce by wri t i ng i n t o i n t e rnal cont rol regi st er. (see st ep 1 t h rough 4 for w r ite operat i on) lcc-8 package drawing hermetica lly s e a l ed pa cka g e ou tlin e
|
